[ Source: verilator ]
Paketti: verilator (4.038-1)
Links for verilator
Trisquel-palvelut:
Imuroi lähdekoodipaketti verilator:
Ylläpitäjä:
Original Maintainers:
- Debian Electronics Team (Mail Archive)
- أحمد المحمودي (Ahmed El-Mahmoudy)
External Resources:
- Kotisivu [www.veripool.org]
Samankaltaisia paketteja:
fast free Verilog simulator
Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.
Muut pakettiin verilator liittyvät paketit
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- dep: libc6 (>= 2.29)
- GNU C Library: Shared libraries
myös näennäispaketti, jonka toteuttaa libc6-udeb
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- rec: libsystemc-dev
- Development files for SystemC library
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- sug: gtkwave
- VCD (Value Change Dump) file waveform viewer
Imuroi verilator
| Arkkitehtuuri | Paketin koko | Koko asennettuna | Tiedostot |
|---|---|---|---|
| amd64 | 4,621.2 kt | 20627 kt | [tiedostoluettelo] |
| arm64 | 4,091.2 kt | 19751 kt | [tiedostoluettelo] |
| armhf | 3,676.3 kt | 12916 kt | [tiedostoluettelo] |
| ppc64el | 4,628.8 kt | 24355 kt | [tiedostoluettelo] |