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Balík: covered (0.7.10-3build1)

Verilog code coverage analysis tool

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

Ostatné balíky súvisiace s balíkom covered

  • závisí
  • odporúča
  • navrhuje
  • dep: libc6 (>= 2.11)
    GNU C Library: Shared libraries
    tiež virtuálny balík poskytovaný balíkom libc6-udeb
  • dep: libtcl8.6 (>= 8.6.0)
    Tcl (the Tool Command Language) v8.6 - run-time library files
  • dep: libtk8.6 (>= 8.6.0)
    Tk toolkit for Tcl and X11 v8.6 - run-time files
  • dep: tklib
    standard Tk Library
  • dep: zlib1g (>= 1:1.1.4)
    compression library - runtime
  • rec: iverilog
    Icarus verilog compiler
    alebo verilog
    Icarus verilog compiler (transitional package)
    alebo gplcver (>= 2.12a-1.1)
    Verilog simulator

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i386 533.6 kB2506 kB [zoznam súborov]