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[ Paquet source : arachne-pnr  ]

Paquet : arachne-pnr (0.1+20160813git52e69ed-1)

Place and route tool for iCE40 family FPGAs

Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It accepts as input a technology-mapped netlist in BLIF format, as output by the Yosys synthesis suite for example. It currently targets the Lattice Semiconductor iCE40 family of FPGAs. Its output is a textual bitstream representation for assembly by the IceStorm icepack command. The output of icepack is a binary bitstream which can be uploaded to a hardware device.

Together, Yosys, arachne-pnr and IceStorm provide an fully open-source Verilog-to-bistream tool chain for iCE40 1K and 8K FPGA development.

Autres paquets associés à arachne-pnr

  • dépendances
  • recommandations
  • suggestions
  • dep: arachne-pnr-chipdb
    Chip db files for arachne-pnr
  • dep: fpga-icestorm
    Tools to handle the bitstream format of Lattice iCE40 FPGAs
  • dep: libc6 (>= 2.14)
    GNU C Library: Shared libraries
    un paquet virtuel est également fourni par libc6-udeb
  • dep: libgcc1 (>= 1:3.0)
    GCC support library
  • dep: libstdc++6 (>= 5.2)
    GNU Standard C++ Library v3
  • dep: yosys
    Framework for Verilog RTL synthesis

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