Package: verilator (3.916-1build1)
Links for verilator
Trisquel Resources:
Download Source Package verilator:
Maintainer:
Original Maintainers:
- Debian Electronics Team (Mail Archive)
- أحمد المحمودي (Ahmed El-Mahmoudy)
External Resources:
- Homepage [www.veripool.org]
Similar packages:
fast free Verilog simulator
Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.
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Download verilator
Architecture | Package Size | Installed Size | Files |
---|---|---|---|
amd64 | 2,811.0 kB | 12811 kB | [list of files] |
i386 | 2,902.7 kB | 11385 kB | [list of files] |