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Package: verilator (4.038-1)

fast free Verilog simulator

Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.

Other Packages Related to verilator

  • depends
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  • dep: libc6 (>= 2.29)
    GNU C Library: Shared libraries
    also a virtual package provided by libc6-udeb
  • sug: gtkwave
    VCD (Value Change Dump) file waveform viewer

Download verilator

Download for all available architectures
Architecture Package Size Installed Size Files
amd64 4,621.2 kB20627 kB [list of files]
arm64 4,091.2 kB19751 kB [list of files]
armhf 3,676.3 kB12916 kB [list of files]
ppc64el 4,628.8 kB24355 kB [list of files]