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Package: opensta (0~20191111gitc018cb2+dfsg-1build1)

Gate-level Static Timing Analyzer

After synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a Tcl interface for entering commands for analysing designs.

It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design.

Other Packages Related to opensta

  • depends
  • recommends
  • suggests
  • dep: libc6 (>= 2.29)
    GNU C Library: Shared libraries
    also a virtual package provided by libc6-udeb
  • dep: libgcc-s1 (>= 3.0) [not armhf]
    GCC support library
    dep: libgcc-s1 (>= 3.5) [armhf]
  • dep: libreadline8 (>= 6.0)
    GNU readline and history libraries, run-time libraries
  • dep: libstdc++6 (>= 6)
    GNU Standard C++ Library v3
  • dep: libtcl8.6 (>= 8.6.0)
    Tcl (the Tool Command Language) v8.6 - run-time library files
  • dep: zlib1g (>= 1:1.1.4)
    compression library - runtime

Download opensta

Download for all available architectures
Architecture Package Size Installed Size Files
amd64 791.6 kB3782 kB [list of files]
arm64 716.0 kB3669 kB [list of files]
armhf 644.6 kB2479 kB [list of files]
ppc64el 999.9 kB5625 kB [list of files]