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Package: arachne-pnr (0.1+20190728gitc40fb22-2)

Place and route tool for iCE40 family FPGAs

Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It accepts as input a technology-mapped netlist in BLIF format, as output by the Yosys synthesis suite for example. It currently targets the Lattice Semiconductor iCE40 family of FPGAs. Its output is a textual bitstream representation for assembly by the IceStorm icepack command. The output of icepack is a binary bitstream which can be uploaded to a hardware device.

Together, Yosys, arachne-pnr and IceStorm provide an fully open-source Verilog-to-bistream tool chain for iCE40 1K and 8K FPGA development.

The authors of arachne-pnr have now prepared its successor 'nextpnr'.

Other Packages Related to arachne-pnr

  • depends
  • recommends
  • suggests
  • dep: arachne-pnr-chipdb
    Chip db files for arachne-pnr
  • dep: fpga-icestorm
    Tools to handle the bitstream format of Lattice iCE40 FPGAs
  • dep: libc6 (>= 2.29)
    GNU C Library: Shared libraries
    also a virtual package provided by libc6-udeb
  • dep: libgcc-s1 (>= 3.0) [not armhf]
    GCC support library
    dep: libgcc-s1 (>= 3.5) [armhf]
  • dep: libstdc++6 (>= 5.2) [armhf]
    GNU Standard C++ Library v3
    dep: libstdc++6 (>= 9) [not armhf]
  • dep: yosys
    Framework for Verilog RTL synthesis
  • sug: nextpnr
    Package not available

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Download for all available architectures
Architecture Package Size Installed Size Files
amd64 207.0 kB665 kB [list of files]
arm64 181.2 kB577 kB [list of files]
armhf 181.5 kB396 kB [list of files]
ppc64el 206.6 kB729 kB [list of files]